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Philips Semiconductors Linear Products
Product specification
10-Bit high-speed multiplying D/A converter
NE/SE5410
DESCRIPTION
The NE5410/SE5410 are 10-bit Multiplying Digital-to-Analog Converters pin- and function-compatible with the industry-standard MC3410, but with improved performance. These are capable of high-speed performance, and are used as general-purpose building blocks in cost effective D/A systems. The NE/SE5410 provides complete 10-bit accuracy and differential non-linearity over temperature, and a wide compliance voltage range. Segmented current sources, in conjunction with an R/2R DAC, provide the binary weighted currents. The output buffer amplifier and voltage reference have been omitted to allow greater speed, lower cost, and maximum user flexibility.
PIN CONFIGURATION
F Package
VEE 1 GND 2 OUTPUT 3 D1 (MSB) 4 D2 5 D3 6 D4 7 D5 8 16 VREF+ 15 V -
REF 10
14 V CC 13 D (LSB) 12 D9 11 D8 10 D7 9 D6
TOP VIEW
FEATURES
* Pin- and function-compatible with MC3410 * 10-bit resolution and accuracy (0.05%) * Guaranteed differential non-linearity over temperature * Wide compliance voltage range---2.5 to +2.5V * Fast settling time--250ns typical * Digital inputs are TTL- and CMOS-compatible * High-speed multiplying input slew rate--20mA/s * Reference amplifier internally-compensated * Standard supply voltages +5V and -15V
APPLICATIONS
BLOCK DIAGRAM
MSB LSB D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 4 5 6 7 8 9 10 11 12 13 3 CURRENT SWITCHES IO
LADDER TERMINATORS
R-2R LADDER
* Successive approximation A/D converters * High-speed, automatic test equipment * High-speed modems * Waveform generators * CRT displays * Strip CHART and X-Y plotters * Programmable power supplies * Programmable gain and attenuation
ORDERING INFORMATION
DESCRIPTION 16-Pin Ceramic Dual In-Line Package (CERDIP) 16-Pin Ceramic Dual In-Line Package (CERDIP)
VREF(+) VREF(-)
16 15 BIAS CIRCUITRY REFERENCE CURRENT AMPLIFIER 1 VEE 2 GND 14 VCC
TEMPERATURE RANGE 0 to +70C -55 to +125C
ORDER CODE NE5410F SE5410F
DWG # 0582B 0582B
August 31, 1994
767
853-0945 13721
Philips Semiconductors Linear Products
Product specification
10-Bit high-speed multiplying D/A converter
NE/SE5410
ABSOLUTE MAXIMUM RATINGS
TA=+25C, unless otherwise specified. SYMBOL VCC VEE VI VO IREF(16) VREF VREF(D) TA Digital input voltage Applied output voltage Reference current Reference amplifier inputs Reference amplifier differential inputs Operating temperature range SE5410 NE5410 TJ TSTG PD Junction temperature Ceramic package Storage temperature Maximum power dissipation TA=25C (still-air)1 +150 -65 to +150 1190 C C mW -55 to +125 0 to +70 C C Power supply PARAMETER RATING +7.0 -18 +15 +4, -5.0 2.5 VCC, VEE 0.7 UNIT VDC VDC VDC VDC mA VDC VDC
NOTES: 1. Derate above 25C at the following rate: F package at 9.5mW/C
DC ELECTRICAL CHARACTERISTICS (Continued)
VCC=+5.0VDC, VEE=-15VDC, IREF=2.0mA, all digital inputs at high logic level. SE5410: TA=-55C to +125C, NE5410 Series: TA=0C to +70C, unless otherwise noted. SYMBOL R PARAMETER Relative accuracy (Error relative to full scale IO) Differential non-linearity Settling time to within 1/2 LSB (all bits low to high) Propagation delay time Output full-scale current drift Digital input logic levels (all bits) High level, Logic "1" Low level, Logic "0" Digital input current (all bits) High level, VIH = 5.5V Low level, VIL = 0.8V Reference input bias current (Pin 15) Output current (all bits high) Output currents (all bits low) Output voltage compliance Reference amplifier slew rate Reference amplifier settling time Output current power supply sensitivity Output capacitance VO = 0 0 to 4.0mA, 0.1% VREF = 2.000V, R16 = 1000 TA = 25C TA = 25C R < 0.050% relative to full-scale 20 2.0 0.003 25 0.01 3.937 -1.0 3.996 0 2.0 Over temperature TEST CONDITIONS Over Temperature LIMITS Min Typ 0.025 1/4 0.025 1/4 tS tPLH tPHL TCIO VIH TA = 25C TA = 25C 250 35 20 20 40 Max 0.05 1/2 0.05 1/2 UNIT % LSB % LSB ns ns ppm/C VDC 0.8 20 -20 -5.0 4.054 0.4 -2.5 +2.5 A A mA A VDC mA/s s %/% pF
IIH IIL IREF(15) IOH IOL VO SR IREF ST IREF PSRR(-) CO
August 31, 1994
768
Philips Semiconductors Linear Products
Product specification
10-Bit high-speed multiplying D/A converter
NE/SE5410
DC ELECTRICAL CHARACTERISTICS
VCC=+5.0VDC, VEE=-15VDC, IREF=2.0mA, all digital inputs at high logic level. SE5410: TA=-55C to +125C, NE5410 Series: TA=0C to +70C, unless otherwise noted. SYMBOL CI ICC IEE VCC VEE PARAMETER Digital input capacitance (all bits high) Power supply current (all bits low) Power supply voltage range Power consumption TA = 25C VO = 0 +4.75 -14.25 TEST CONDITIONS LIMITS Min Typ 4.0 +2 -12 +5.0 -15 190 +4 -18 +5.25 -15.75 300 Max UNIT pF mA VDC mW
4.0 ICC IEEPOWER SUPPLY CURRENT (mA) 13 12 11 10 4 3 2 1 0 -75 -50 -25 +ICC +VCC = +5V -VEE = -15V IREF = 2mA IEE OUTPUT CURRENT (mA)
3.0 +VCC = +5V 2.0 -VEE = -15V TA = 25C 1.0 IREF = 2mA
0
-1.0 -5 -3 -1 0 1 3 COMPLIANCE VOLTAGE (VOLT) 5
0
25
50
75 100 125
TA (C)
Figure 1. Output Current vs Output Compliance Voltage
OUTPUT COMPLIANCE VOLTAGE (VOLTS) 4.0 3.0 2.0 1.0 0 -1.0 -2.0 -3.0 -4.0 -75 -50 -25 +VCC = +5V -VEE = -15V IREF = 2mA
Figure 3. Power Supply Currents vs Temperature
0
25
50
75 100 125
TA (C)
Figure 2. Maximum Output Compliance Voltage vs Temperature
Figure 4. Reference Amplifier Frequency Response An on-chip high slew reference current amplifier drives the R/2R ladder and segment decoder. The currents are scaled in such a way that, with all bits on, the maximum output current is two times 1023/1024 of the reference amplifier current, or nominally 3.996mA for a 2.000mA reference input current. The reference amplifier allows the user to provide a voltage input: out-board resistor R16 (see Figure 6) converts this voltage to a usable current. A current mirror doubles this reference current and feeds it to the segment decoder and resistor ladder. Thus, for a reference voltage of 2.0V and a 1k resistor tied to Pin 16, the full-scale current is
CIRCUIT DESCRIPTION
The NE5410 consists of four segment current sources which generate the 2 Most Significant Bits (MSBs), and an R/2R DAC implemented with ion-implanted resistors for scaling the remaining 8 Least Significant Bits (LSBs) (see Figure 5). This approach provides complete 10-bit accuracy without trimming. The individual bit currents are switched ON or OFF by fully-differential current switches. The switches use current steering for speed.
August 31, 1994
769
Philips Semiconductors Linear Products
Product specification
10-Bit high-speed multiplying D/A converter
NE/SE5410
approximately 4.0mA. This relationship will remain regardless of the reference voltage polarity. Connections for a positive reference voltage are shown in Figure 6a. For negative reference voltage inputs, or for bipolar reference voltage inputs in the multiplying mode, R15 can be tied to a negative voltage corresponding to the minimum input level. For a negative reference input, R16 should be grounded (Figure 6b). In addition, the negative voltage reference must be at least 3V above the VEE supply voltage for best operation. Bipolar input signals may be handled by connecting R16 to a positive voltage equal to the peak positive input level at Pin 15. When a DC reference voltage is used, capacitive bypass to ground is recommended. The 5V logic supply is not recommended as a reference voltage. If a well regulated 5.0V supply, which drives logic, is to be used as the reference, R16 should be decoupled by connecting it to the +5.0V logic supply through another resistor and
(4) MSB D1 (5) D2 (6) D3 (7) D4
bypassing the junction of the two resistors with a 0.1F capacitor to ground. The reference amplifier is internally-compensated with a 10pF feed-forward capacitor, which gives it its high slew rate and fast settling time. Proper phase margin is maintained with all possible values of R16 and reference voltages which supply 2.0mA reference current into Pin 16. The reference current can also be supplied by a high impedance current source of 2.0mA. As R16 increases, the bandwidth of the amplifier decreases slightly and settling time increases. For a current source with a dynamic output impedance of 1.0M, the bandwidth of the reference amplifier is approximately half what it is in the case of R16=1.0k, and settling time is 10s. The reference amplifier phase margin decreases as the current source value decreases in the case of a current source reference, so that the minimum reference current supplied from a current source is 0.5mA for stability.
(13) LSB D10 GND (2)
(8) D5
(9) D6
(10) D7
(11) D8
(12) D9
IOUT (3) SEGMENT DECODER
VBIAS (INTERNAL)
2R
2R
2R
2R
2R
2R
2R
2R
R
R
R
R
R
R
(16) + VREF + CODE SELECTED 0111110011 (15) - - 2R1 R1 R1 R1 R1
VEE (1)
Figure 5. NE5410 Equivalent Circuit
August 31, 1994
770
Philips Semiconductors Linear Products
Product specification
10-Bit high-speed multiplying D/A converter
NE/SE5410
VR (+)
RT R16 VCC D1 THROUGH D10 14 16 R15 15 IO 5410 3
and full-scale current drift. Relative accuracy, or linearity, is the measure of each output current with respect to its intended fraction of the full-scale current. The relative accuracy of the NE5410 is fairly constant over temperature due to the excellent temperature tracking, of the implanted resistors. The full-scale current from the reference amplifier may drift with temperature causing a change in the absolute accuracy. However, the NE5410 has a low full-scale current drift with temperature. The SE5410 and the NE5410 are accurate to within LSB at 25C with a reference current of 2.0mA on Pin 16.
1 2 NOTES: VEE R16 + RT = R15 = RREF RT < MONOTONICITY
The NE5410 and SE5410 are guaranteed monotonic over temperature. This means that for every increase in the input digital code, the output current either remains the same or increases but never decreases. In the multiplying mode, where reference input current will vary, monotonicity can be assured if the reference input current remains above 0.5mA.
R16 15 IO
VR (-)
RT VCC R15 13
SETTLING TIME
The worst-case switching condition occurs when all bits are switched "on," which corresponds to a LOW-to-HIGH transition for all bits. This time is typically 250ns for the output to settle to within 1/2LSB for 10-bit accuracy, and 200ns for 8-bit accuracy. The turn-off time is typically 120ns. These times apply when the output swing is limited to a small (<0.7V) swing and the external output capacitance is under 25pF. The major carry (MSB off-to-on, all others on-to-off) settles in approximately the same time as when all bits are switched off-to-on. If a load resistor of 625 is connected to ground, allowing the output to swing to -2.5V, the settling time increases to 1.5s. Extra care must be taken in board layout as this is usually the dominant factor in satisfactory test results when measuring settling time. Short leads, 100F supply bypassing, and minimum scope lead length are all necessary. A typical test setup for measuring settling time is shown in Figure 7. The same setup for the most part can be used to measure the slew rate of the reference amplifier (Figure 9) by tying all data bits high, pulsing the voltage reference input between 0 and 2V, and using a 500 load resistor RL.
D1 THROUGH D10 NOTES: R15 + RT = R16 RT < 5410
2
b. Negative Reference Voltage
Figure 6. Basic Connections
OUTPUT VOLTAGE COMPLIANCE
The output voltage compliance ranges from -2.5 to +2.5V. As shown in Figure 2, this compliance range is nearly constant over temperature. At the temperature extremes, however, the compliance voltage may be reduced if VEE>-15V.
ACCURACY
Absolute accuracy is a measure of each output current level with respect to its intended value. It is dependent upon relative accuracy
August 31, 1994
771
Philips Semiconductors Linear Products
Product specification
10-Bit high-speed multiplying D/A converter
NE/SE5410
VCC 0.1F
+2VDC 14 4 5 6 7 8 9 10 11 12 13 VI 50 1 0.1F 2 NE5410 3 500 VO 0 CO 25pF tS -- 250ns TYPICAL TO 1/2 LSB 15 1k RL 0.5V 0.1F 16 1k 2.4V VI 0.4V RISE AND FALL TIMES 10ns
VO
VEE
Figure 7. Settling Time
VCC 0.1F
14 4 5 6 7 8 9 10 11 12 13 VI 50 1 0.1F -80mV TO 1/2 LSB tPLH VEE FOR PROPAGATION DELAY TIME tPHL 2 RL 20 VO NE5410 3 VO 15 1k 0.1F VI 0.4V 2.4V 16 1k +2VDC RISE AND FALL TIMES 10ns
0V
Figure 8. Propagation Delay Time
August 31, 1994
772
Philips Semiconductors Linear Products
Product specification
10-Bit high-speed multiplying D/A converter
NE/SE5410
VCC 0.1F
VREF (+) 14 4 5 6 7 8 9 10 11 12 13 1 0.1F 2 25pF NE5410 3 15 1k RL 500 0.1F 16 1k
2V 0 VREF (+)
2.0V
0 0.5V VO SLEW RATE 0 tS = 2s TYPICAL TO 0.1%
VO
NOTE: Use RL = 20 to GND for slew rate measurement.
VEE
Figure 9. Reference Amplifier Settling Time and Slew Rate
F.S. ADJ 5V REF 2.5k VCC 2.5k 16 5410 15 1/2 NE5535 2.5k VEE 0.1F 0 ADJ VOUT +15V 0.1F RT RF
RREF
10k
-15V
Figure 10. Bipolar Voltage Output Circuits (-10V to +10V)
August 31, 1994
773
Philips Semiconductors Linear Products
Product specification
10-Bit high-speed multiplying D/A converter
NE/SE5410
5V REF
2.4k F.S. ADJ +5VDC 200 16 2.5k 15 NE5410
ANALOG INPUT (0-10V) 20k -V 2.5k 3 ZERO ADJ 500k 3 +V 1 V1+ IN A 14 V2+ +5VDC
NE529 2.5k -15VDC DOUT Q9 2504 SAR CLOCK CP Q0 4 IN B 6 -10VDC D S START EOC OUT A 10
E
Q10
+5VDC NOTES: 10-bit conversion time = 3.3s with 3MHz clock. This converter uses a 2504 12-bit successive approximation register in the short cycle operating mode where the end of conversion signal is taken from the first unused bit of the SAR (Q10).
Figure 11. Successive Approximation A/D Converter
7 6 5 P BUS 4 3 2 1 0 CONTROL SIGNALS FROM P E2 E1 1D 0 7 D1 Q0 2 Q1 6 1/2 LS375 E0,1 4
19 16 15 12 9 6 5 2
1 OE
LS373 NE5410
E2,3
Q2 Q3
11
1/2LS375 13
TIMING SEQUENCE E1 E2 DATA
NOTES: With this double latch technique, valid data will be latched to the DAC until updated with the E 2 pulse. Timing will depend on the processor used.
August 31, 1994
EE E EE EE E EE EE E EE
DB0,1 DB2-9
Figure 12. 8-Bit P Bus Interface
774
Philips Semiconductors Linear Products
Product specification
10-Bit high-speed multiplying D/A converter
NE/SE5410
VIN
+5V 3k RT ZERO ADJ 3k
5V REF 2.5k 16 2.5k 15 LSB DOUT
VCC 14
VEE 1 2 3 + COMP RI
TTL CLOCK
NE5410
13 12 11 10 9
8
7
6
5
4 MSB -
Q0 START RST 10-BIT COUNTER
Q9 CP -15
NOTE: V IN FULL SCALE + 4mA (R 1 ) R ) T 1023 1024
Figure 13. Staircase A/D
August 31, 1994
775

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